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Processor: Xilinx "Zynq" XC7007S / XC7Z010 / XC7Z020
BORA is the top-class Single and Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems, based on the recent Xilinx "Zynq" XC7Z007S / XC7Z014S / XC7Z010 / XC7Z020 application processor.
BORA offers great computational power, thanks to the rich set of peripherals, the Dual Cortex-A9 and the Artix-7 FPGA inside.
BORA is designed in order to keep full compatibility with the Ultra Line CPU modules, to guarantee the premium quality and technical value of those customers that requires top performances.
You can download BORA SOM brochure by clicking here.
To get a quote you can contact DAVE Embedded Systems by clicking here.
BORA is a top-class Single and Dual Cortex-A9 + FPGA CPU module based on Xilinx "Zynq" XC7Z007S / XC7Z014S / XC7Z010 / XC7Z020 application processor.
The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:
The processors in the PS always boot first, allowing a software centric approach for PL system boot and PL configuration. The PL can be configured as part of the boot process or configured at some point in the future. Additionally, the PL can be completely reconfigured or used with partial, dynamic reconfiguration (PR). PR allows configuration of a portion of the PL. This enables optional design changes such as updating coefficients or time-multiplexing of the PL resources by swapping in new algorithms as needed.
BORA can mount two versions of the Zynq processor. On this page you can find the table of the comparison between the processor models.
The use of this processor enables extensive system-level differentiation of new applications in many industry fields where high-performance and extremely compact form factor (85mm x 50mm) are key factors.
Yes. BORA Evaluation Kit is the official support platform for evaluation the BORA SOM. It includes a SOM and all the necessary for the fast and easy evaluation.
Here you can find the video of the unboxing of the BORA SOM Evaluation Kit that shows you how the Evaluation Kit is composed and how to unbox and connect it to your development platform.
BORA allows customers to save time and resources by using a compact solution (85mm x 50mm) that includes both a CPU and an FPGA, avoiding complexities on the carrier PCB. Smarter system designs are made possible, following the trends in functionalities and interface of the new, state-of-the-art embedded products.
BORA offers great computational power thanks to the rich set of peripherals, the Dual Cortex-A9 and the Artix-7 FPGA together with a large set of high-speed I/Os (up to 5GHz).
BORA enables designers to create rugged products suitable for harsh mechanical and thermal environments, allowing for the development of the most advanced and robust products.
On this page you can find BORA SOM 3D model.
On this page you can find BORA SOM block diagram.
On this page you can find BORA SOM hardware manual.
On this page you can find all the BORA SOM marketing documentation available.
BORA SOM module part number is identified by the digit-code table that you can find here.
The ZYNQ family is included in the Longevity program by Xilinx. The first ZYNQ SOC used on BORA SOM were released after 2011.
DAVE Embedded Systems is committed to provide its products at least for the same period declared by the silicon vendor. DAVE Embedded Systems manages the components' obsolescence and components through a PCN program according to JEDEC standard (where possible) which may require the customer's support.
Once the silicon vendor provides the LBO (Last Buy Order) and LBS (Last Buy Shipment) for its products DAVE Embedded Systems provide the same documentation to its customers in order to program the product life termination.
DAVE Embedded Systems is available to continue producing the product (procuring material from aftermarket) until the quality is granted and/or until the customer accepts the extra costs related to this process.
DAVE Embedded Systems' goal is to grant the production continuity to its customer including the possibility to redesign its products in order to maintain the product continuity.
If you want to request support to our technical team please fill this form. After the submission, a ticket will be assigned. Our technicians will look after your request and, typically, they will respond you via email within 24 hours from the request.
Here you can find the DAVE Embedded Systems' Return Material Authorization form.
Yes. You can download a PDF version of BORA SOM hardware manual by clicking here.
BORA SOM’s processor and memory subsystem are composed by the following components:
For further information, see this page.
Yes. The PCB version is copper printed on PCB itself and the serial number is printed on a white label (please see here for further information).
Also, a ConfigID is used by software running on the board for the identification of the product model/hardware configuration. Refer to this link for more details.
Here you can find the connectors and pinout description of the BORA SOM.
Implementing correct power-up sequence for Zynq-based system is not a trivial task because several power rails are involved. BORA SOM simplifies this task by embedding all the needed circuitry. Here you can find a simplified block diagram of PSU/voltage monitoring circuitry.
The recommended power-up sequence is:
For further information, see this page.
Here you can find a block diagram of reset scheme and voltage monitoring.
Here you can find information about the Programmable Logic (PL) initialization signals: PROGRAM_B, INIT_B, and DONE.
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot process is multi-stage and minimally includes the Boot ROM and the first-stage boot loader (FSBL). The Zynq-7000 AP SoC includes a factory-programmed Boot ROM that is not useraccessible.
The boot ROM:
After a system reset, the system automatically sequences to initialize the system and process the first stage boot loader from the selected external boot device. The process enables the user to configure the AP SoC platform as needed, including the PS and the PL. Optionally, the JTAG interface can be enabled to give the design engineer access to the PS and the PL for test and debug purposes.
For further information about BORA SOM boot options, please check out more by clicking here.
Here you can find BORA SOM’s maximum ratings, recommended ratings and power consumption.
BORA product is designed to support the maximum available temperature range declared by the manufacturer. The customer shall define and conduct a reasonable number of tests and verification in order to qualify the DUT capabilities to manage the heat dissipation.
Any heatsink, fan etc shall be defined case by case depending on the various use conditions like: air cooling (forced or not), enclosure dimensions, mechanical/thermal coupling with heatsink. A proper thermal analysis must be investigated on the real use scenario which depends on FPGA design, frequency configurations, working signals, etc.
Here you can find the mechanical characteristics of BORA SOM.
Yes. BORA Embedded Linux Kit (BELK in short) provides all the necessary components required to set up the developing environment to:
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