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NXP i.MX95 - AIDA SOM

Processor: NXP i.MX95

PREVIEW

 

The i.MX 95 family is designed to address next‑generation edge computing, advanced vision processing, and high‑performance industrial applications requiring strong security and real‑time determinism. It targets demanding use cases in Smart Industry, robotics, autonomous systems, and edge AI, combining high compute capability with powerful heterogeneous acceleration. One of the most relevant capabilities is the integrated Neural Processing Unit (NPU), which can be seamlessly leveraged thanks to DAVE Embedded Systems’ extensive expertise in deploying Machine Learning workloads on embedded platforms.

The main customization provided by DAVE Embedded Systems will include:

  • Machine Learning NPU‑ready platforms: DAVE Embedded Systems has strong competences in Edge AI and supports customers in defining and tuning the optimal NPU configuration for their specific workload. Our team can help accelerate model deployment, quantization, and optimization for the i.MX 95 AI engine.

  • Secure product design leveraging advanced hardware security: Using our Secure Boot integration competences combined with NXP’s EdgeLock security framework available on the i.MX 95, we enable robust, scalable protection against modern attack vectors. This architecture establishes a hardware Root of Trust and provides end‑to‑end security—from device to cloud—without the need for customers to implement complex security code.

  • AMP (Asymmetric Multi‑Processing) between Cortex‑A and Cortex‑M cores: The heterogeneous architecture of the i.MX 95 enables a clean partitioning between high‑level Linux workloads and deterministic real‑time tasks running on the Cortex‑M. DAVE Embedded Systems supports AMP configuration, communication channels, and system integration.

  • Board optimization for Vision and high‑bandwidth peripherals: Thanks to the i.MX 95 advanced imaging capabilities—including multi‑camera support, integrated ISPs, and high‑speed interfaces—our designs can be tailored for demanding vision systems. Dual Gigabit Ethernet with TSN support enables deterministic networking, ideal for industrial and robotics environments.

Block Diagram

Datasheet

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Technical Information

CPU
  • NXP i.MX956 / 952
  • Quad ARM Cortex-A55
  • MCU Cortex-M33
Video
  • 3D GPU
  • 1080p60 H265, H264, VP9, VP8 decoder
  • 1080p60 H265, H264 encoder
Machine
Learning
  • Neural Processing Unit 2.3 TOPS
Supervisor
  • On-board power supply supervision
  • and power sequencer; Watchdog and RTC
Cache
  • L1: 32Kbyte instruction, 32Kbyte data
  • L2: Unified data/instruction, 512 K
Security
  • Secure Boot and secure enclave
Memory
  • SDRAM: Up to 8GB LPDDR5, x32 with ECC
  • NOR: SPI NOR 4 - 32 MB on request
  • eMMC: All sizes, on request. Not available simultaneously
Interfaces
  • LAN: Ethernet 10/100/1000 Mbps (PHY on board) 1xRGMII with TSN support
  • UART: up to 4x UART ports
  • USB: up to 2x 3.0 OTG port (PHY on board)
  • CAN: up to 2x CAN
  • SDIO: up to 2x SDIO3.0 - MMC 5.1
  • Audio: Up to 18 I²S / SAI and 1x SPDIF
  • Video Output:
    • 1x LVDS 4/8 lanes
    • 1x MIPI DSI
    • 1x HDMI
  • Video Input: 2x MIPI CSI 4 lanes with 2xISP
  • PCI express: 1x PCIe Gen 3
  • Other:
    • up to 6x I2C channels
    • up to 3x SPI channels
    • GPIOs with interrupt capabilities
Mechanical
  • Connectors: SODIMM DDR4 260pins
  • Size: 69.60mm x 43.00mm
  • Temperature range:
    • Commercial (0°C / +70°C) temperature range
    • Industrial (-40°C / +85°C) temperature range
Power Supply
  • Single 3.3V +/- 5%, on-board voltage regulation with power good enabling

 

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