Application notes

Video processing and hardware/software partitioning


This white paper describes a video processing system - built upon BORA / BORA EVB - that satisfies specific functional and safety requirements. The implementation combines different techniques that are available on Zynq platform, to implement a hardware/software partitioning meeting these requirements.

Non-intrusive continuous multi-gigabit transceivers link monitoring


This White Paper describes a practical application of the asymmetric multi-processing (AMP) configuration. Specifically, this approach has been used to implement a non-intrusive continuous link monitoring mechanism for the Xilinx Zynq multi-gigabit serial transceivers.

Enabling dual Gigabit Ethernet support on Xilinx Zynq EVB


The aim of this Application Note is to describe how to integrate a second Ethernet port on the BORA EVB. This application note describes how to implement such configuration, providing a reference design for Vivado 2014.4 and linux kernel configuration instructions.

Interfacing BoraEVB to thin film electroluminescent display


The following Application Note describes how to interface BORA Xilinx Zynq SoM to a Lumineq display. The target of this AN is to demonstrate how a Xilinx Zynq SOM can control/drive a Lumineq display by using its FPGA.

The demo is based on Xilinx Zynq but it is possible to interface the same display with other platforms (such as Freescale i.MX6 and Texas Instruments AM335) by adding some HW control logic. DAVE Embedded Systems is availble for supporting customers on this activities.

Real-timeness, system integrity and TrustZone® technology on AMP configuration


This white paper is a sequel of AN-BELK-001 and describes how to improve the standard AMP configuration within a complete division between the General Purpose O.S. and the Real Time O.S.
The RTOS is completely indipendent and has full control over GPOS.

Interfacing Xilinx Zynq EVB to TFT LCD display



This Application Note describes how to interface a popular LCD display model (Ampire AM-800480STMQW-TA1) to DAVE Embedded Systems' BoraEVB starting from the availability of a LCD controller in its Xilinx Zynq-based engine (FPGA IP).

Interfacing DDR3 SDRAM to PL


CPU modules are characterized by direct addressing of hardware resources: NOR, NAND and RAM. BORA CPU module is not an exception.
However, in some scenarios it might be required to address also a secondary RAM bank dedicated to additional buffers or graphic memory.
To achieve that, users are supposed to design an IP in the programmable logic (PL) of Zynq and reserve a dedicated bank in FPGA to guarantee exclusive access and to maximize bandwidth.
Moreover, this additional SDRAM bank is accessible via AXI bus and it is mapped in the processor's memory space, thus it can be accessed by the Zynq's PS as well.
BoraEVB can optionally be populated with a 16-bit 512MB SDRAM chip that is directly connected to PL.
This Application Note describes how to enable the support for this additional memory bank. An example Vivado design is released along with this application note, based on BELK 2.1.0

Asymmetric Multiprocessing (AMP) on Axel – Linux + FreeRTOS


This application note describes in detail the implementation of Linux/FreeRTOS asymmetric multiprocessing configuration on DAVE Embedded Systems AXEL LITE. This configuration is a typical example about how to leverage AMP flexibility to combine, on one single piece of silicon, the versatility of Linux o.s. for general purpose computation, connectivity and HMI and the determinism of an RTOS to satisfy real-time constraints. Since AXEL family products are all based on Freescale i.MX6 processors, what here described applies to AXEL ULTRA too. About debugging, AMP systems pose new challenges to software developers because multiple operating systems need to be debugged at the same time. The second part of this application note - written in collaboration with Lauterbach Srl-shows some advanced debugging techniques addressing these issues.

Asymmetric Multiprocessing (AMP) on Bora – Linux + FreeRTOS


This application note describes how to run a simple application on FreeRTOS porting for Zynq, running on Zynq core #2.
BORA is the new top-class Dual Cortex-A9 + FPGA CPU module by DAVE Embedded Systems, based on the recent Xilinx Zynq XC7Z010/XC7Z020 application processor. Thanks to BORA, customers are going to save time and resources by using a compact solution that includes both the CPU and the FPGA, avoiding complexities on the carrier PCB.

Trace on the Bora AMP (Linux + FreeRTOS) system


This application note describes how to configure TRACE32 ® debugger to support debugand trace of Linux running on the first Zynq core, and FreeRTOS, running on the second Zynq core.
This application note is the proper continuation of the previously releseased AN-BELK-001 “AMP on Bora - Linux and FreeRTOS”, which describes how to build the software components required to set up asymmetric multi-processing (AMP)” on Bora.

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