Products and Technologies for Embedded Systems and Networking

2009-04-21

FPGA details

FPGA IP Cores

The following table reports the available FPGA IP Cores for our CPU modules:

Peripheral	Description	Qong	Neptune	Aria
Ethernet 10/100/1000	Ethernet Media Access Controller supporting 10/100/1000 Mpbs links	Yes (10/100 only)	Yes	Yes
UART 16550	16550 software compatible UART	Yes	Yes	Yes
PCI to WB	PCI to Wishbone bridge	N.A.	Yes	N.A.
DRED Intercon	This module allows to build a super PCI device embedding several peripheral modules (16550 UART, Ethernet Tri-Speed MAC etc.)	N.A.	Yes	N.A.
GPIO	General purpose I/O controller	Yes	Yes	Yes
WB to 8051-like bus	This core allows to generate 8051-like bus accesses in order to interface host processor to legacy devices such as SJA1000 CAN controller. On FPGA side, it interfaces to Wishbone bus.	Yes	Yes	Yes
WB to static bus	This core implements a static memory controller that is able to interface to SRAM-like devices. On FPGA side, it interfaces to Wishbone bus.	Yes	Yes	Yes
EMB to WB	Freescale MCP5121 EMB-to-Wishbone bridge.	N.A.	N.A.	Yes
Freescale MPC5121 power and reset manager	This core implements a finite state machine used to generate the power sequence and handle reset signals required by Freescale MPC5121 processor.	N.A.	N.A.	Yes
Local bus to WB	This core implements a bridge used to interface host processor bus (address/data/control) to Wishbone bus.	Yes	N.A.	N.A.
Simple Wishbone intercon	Wishbone intercon implementation supporting 1 master and N slaves. For more details, please see also http://www.opencores.org/downloads/wbspec_b3.pdf	Yes	N.A.	Yes

IP CORES distribution models

Development kits provide a default FPGA configuration that can be used as is to build user's application.

In case it is required to customize it, the following distribution models are available:

DAVE provides FPGA bitstream customized on the customer specifications. DAVE takes on the integration work.
IP cores are delivered as single binaries, in order to allow the customer to include them in his/her FPGA design project. The customer takes on the integration work.
IP cores are delivered as source files, so the customer can include them in his/her FPGA design project. The customer takes on the integration work. This is limited to the in-house developed IPs.

Each solution has costs that may vary, depending on several factors (for example on how many IPs are needed, purchasing volumes, etc.). Please contact our sales department for more information and pricing at sales@dave.eu.